Sense amplifiers are widely used in integrated circuit memory devices to sense a small voltage difference from a memory cell that is being read and to amplify the small difference to one of two binary logic levels. In general, it is desirable for the sense amplifier to sense this voltage difference rapidly and accurately, so that high speed and reliable read operations may be provided in integrated circuit memory devices.
As integrated circuit memory devices become more highly integrated, and are capable of storing more information in a single integrated circuit, the output of the individual memory cells may be reduced. For example, outputs of 20-100 mV may be provided. It is desirable for the sense amplifier to sense these microvoltage differentials rapidly and reliably.
FIG. 1 illustrates a conventional CMOS differential sense amplifier. As shown in FIG. 1, the sense amplifier employs both n-type and p-type metal oxide semiconductor field effect transistors (MOSFETs), also referred to as complementary MOSFETs or CMOS.
Referring now to FIG. 1, input signals IN and INB which correspond to the small voltage differential that is obtained from a sensed memory cell, are respectively provided to first and second input paths. These signals are applied to respective gates of n-type MOSFETs (referred to as NMOS) transistors 6 and 8. A pair of cross-coupled p-type MOSFET transistors (referred to as PMOS) 2 and 4 provide a latch. In particular, the sources of PMOS transistors 2 and 4 are commonly connected to a power supply node and the drains of the respective cross-coupled PMOS transistors 2 and 4 are connected to the drains of NMOS FETs 6 and 8. The drains and gates of PMOS transistors 2 and 4 are cross-coupled to provide a latch. Complementary output signals OUT and OUTB are obtained from the common drain node of MOSFETs 2 and 6 and from the common drain node of MOSFETs 4 and 8.
In operation, a small difference of voltage between the two input nodes IN and INB are amplified and output to the first and second output terminals OUT and OUTB. In particular, in response to a pre-sense amp enable signal PSE, transistors 10 and 12 are activated. Upon sensing a minute differential between input signals IN and INB, the latch comprising cross-coupled transistors 2 and 4 latches to one of two binary values and thereby provides complementary output signals on output terminals OUT and OUTB.
CMOS differential sense amplifiers as shown in FIG. 1 are described in more detail in U.S. Pat. No. 5,155,397 to Fassino et al. entitled "CMOS Differential Sense Amplifier". CMOS differential sense amplifiers as described in FIG. 1 can rapidly perform a sensing operation and can dissipate little power in standby mode. Unfortunately, if a signal is erroneously sensed, the sense amplifier may continuously repeat the erroneous sensing even though proper input signals are provided to the sense amplifier. Moreover, the minimum voltage differential which can be sensed reliably may be a function of the threshold voltage variations between the latch PMOS transistors 2 and 4. In order to overcome threshold voltage mismatches that may occur, sensing of the inputs may be delayed by delaying application of the pre-sense amp enable signal PSE. Thus, it may take an undesirably long time to reliably sense the input signal differential.